This invention relates to a nonvolatile semiconductor memory device, and more particularly to a programmable ROM (read only memory) in which data can be electrically programmed and erased.
Memory cells used in the electrically erasable and programmable ROM are generally expressed as E.sup.2 PROM and have each the structure as shown in FIG. 1.
In the figure, reference numeral 80 designates a P type semiconductor substrate, and reference numeral 81 and N type impurity diffusion layer to be used as a source region. A first insulating film (not shown) is formed on the diffusion layer 81, and first electrode 82 formed of a first polycrystalline silicon layer is formed on the first insulating film. A second insulating film (not shown) is formed on the first electrode 82, and second electrode 83 formed of a second polycrystalline silicon layer is formed on the first and second insulating films. The second electrode 83 extends above diffusion layer 81. Second electrode 83 is electrically floating. A third insulating film (not shown) is formed on an extended portion of second electrode 83. Third electrode 84 formed of a third polycrystalline layer is formed on the third insulating film. The upper surfaces of first and second electrodes 82 and 83 are each of the asperity or texture structure type. Second electrode 83 is a floating gate electrode and third electrode 84 is a control electrode.
Assume that third electrode 84 is set at high potential Vpp, e.g., +20 V, and first electrode 82 and diffusion layer 81 are both set at ground potential GND (0 V). Under these conditions, capacitance-coupling exists between third electrode 84 and second electrode 83, between second electrode 83 and first electrode 82, and between second electrode 83 and diffusion layer 81. Second electrode 83 has a relatively low potential by means of the capacitance-coupling. As a result, if electron charges have been injected into second electrode 83, the charges are discharged from second electrode 83 to third electrode 84, erasing data.
Assume that high potential Vpp is set to third electrode 84 and diffusion layer 81, and ground potential GND is set to first electrode 82. Then, the potential at the second electrode 83 is placed at a relatively high potential. As a result, charges are injected into second electrode 83 from first electrode 82, thus writing data into the memory cell.
Since second electrode 83 is electrically floating, the injected charges are stored. Thus, memory cells structured as shown in FIG. 1 are nonvolatile.
FIG. 2 shows a schematic illustration of an actual memory device including memory cells each having the above structure, arranged in a matrix fashion. In the figure, the memory cells are designated by 90A to 90C, and the matrix is a 3.times.3 matrix for simplicity for illustration.
Third electrode lines 91A to 91C are each common to three memory cells arranged in a row. Source lines 92A to 92C also are each common to three memory cells in a row. First electrode lines 93A to 93C are each common to three memory cells arranged in a column.
A problem with the memory cell matrix wiring shown in FIG. 1 is that half-selected memory cells are present in addition to the selected memory cells. More specifically,to select memory cell 90A, only first electrode line 93B is placed in an "L (low)" state, while first electrode lines 93A and 93C are both in an "H (high)" state, and third electrode line 91B is placed in the "H" state, while third electrode lines 91A and 91C are both in the "L" state. Since first electrode lines 93A and 93C and third electrode line 91B are placed in the "H" state, when the potential of the source wiring 92B is relatively low, a small number of electrons are injected into the second electrode of memory cells 90B. This state is the half-selected state of memory cells 90B. Similarly, since first electrode wiring 93B and third electrode wirings 91A and 91C are placed in the "L" level, when the potential of the source wiring 92C is relatively high, a small number of electrons are injected into the second electrode of memory cells 90C. This state is the half-selected state of memory cells 90C.
As described above, in conventional memory devices using such E.sup.2 PROM, half-selected memory cells are present. When the memory device is used for a long time, erase and rewrite cycles are repeated many times, thus destroying the data in the non-selected memory cells and impairing the reliability of the memory device.